1. Field of the Invention
This invention relates to a semiconductor device, more specifically a semiconductor device being capable of compact its wiring.
2. Description of the Related Art
A vertical type double diffusion metal oxide field effect transistor (D-MOSFET), a kind of power MOSFET is known very well as a semiconductor device for power source to a person skilled in the art. FIG. 12 is a plane view of the D-MOSFET in the prior art. As shown in FIG. 13 illustrating plane P1--P1, the D-MOSFET 2 comprises a drain region D consist of a substrate 4 and an epitaxial growth layer 6, a plurality of channel formation region 8 formed in the epitaxial growth layer 6 and source regions S formed within each of channel formation regions 8 in dough nut shape.
A source wiring 10 made of aluminum is positioned so as to cover center part of the D-MOSFET 2 (see FIG. 12). The source wiring 10 is connected with each of the source regions S through each source contact 12. A source pad 24 is provided with a part of the source wiring 10 (see FIG. 12).
A part of the each channel formation regions 8 functions as channel regions 14. A plurality of gate G made of polysilicon is positioned on each of the channel regions 14 through a gate oxidation layer 16. All the gate G formed on the each of the channel regions 14 are connected each other. A part of the gate G is connected to a gate pad 22 through a gate electrode 18 made of aluminum and a protective resistor 20. Besides, a drain electrode 26 is provided under the substrate 4.
Thus, a high output currency can be obtained between the source pad 24 (see FIG. 12) and the drain electrode 26 by connecting a plurality of the MOSFET in parallel using the gate pad 22 as a control input terminal.
However, since the gate G are connected to the gate electrode 18 in part. So that, voltage drop in accordance with electric resistance of polysilicon is caused around a part located far from the gate electrode 18 (for instance, vicinity of a part P2 in FIG. 12) when a voltage is applied to the gate pad 22. The part located far from the gate electrode 18 can not be operated properly when large amount of voltage drop occurred.
As shown in FIG. 14A and FIG. 14B both of which enlarge vicinity of the part P2, in order to prevent occurrence of voltage drop at the perimeter of the D-MOSFET 2, a perimeter gate wiring 28 made of aluminum having lower electric resistance is composed as follows. The perimeter gate wiring 28 is positioned to vicinity of perimeter of the D-MOSFET 2 thorough a perimeter gate contact 30 so as to contact to a gate perimeter portion 32.
In the same manner, in order to maintain a voltage among the source regions S studded over a wide range, the perimeter diffusion layer 34 is formed in the epitaxial growth layer 6 positioned vicinity of perimeter of the D-MOSFET 2. And the perimeter source wiring 38 made of aluminum is positioned on the perimeter diffusion layer 34 through an insulation layer 40 so as to contact the perimeter source wiring 38 with the perimeter diffusion layer 34 through a perimeter source contact 36.
Thus, it is possible to maintain the gate voltage substantially uniform to all over the chip of D-MOSFET 2 by applying the voltage direct to the gate perimeter portion 32 located far from the gate electrode 18 with the perimeter gate wiring 28 made of aluminum. Also, source voltage can be maintained substantially uniform to all over chip of the D-MOSFET by applying the voltage directly to the perimeter diffusion layer 34 with the perimeter source wiring 38 made of aluminum.
However, the D-MOSFET described in the above has following problem to resolve. It is necessary to provide the perimeter source wiring 38 connected with the perimeter diffusion layer 34 through the perimeter source contact 36 in vicinity of perimeter of the chip. Further to that, the perimeter gate wiring 28 connected with the gate perimeter portion 32 through the perimeter gate contact 30 must be provided in parallel to the perimeter source wiring 38.
In that case, it is necessary to design a width of the perimeter source wiring 38 as a width of tolerance for mis-alignment of the perimeter source contact 36 in addition to a width of the perimeter source contact 36. Also, it is necessary to use same design rule to a width of the perimeter gate wiring 28. Further, it is necessary to design a space having certain width between the perimeter source wiring 38 and the perimeter gate wiring 28 for providing an insulation region 42. So that, a space for these wirings need to be secured in vicinity of perimeter of the chip. Therefore, size of the chip becomes large.